DESCRIPTION
FPGA hardware accelerators are increasingly popular for executing computationally intensive tasks, such as AI algorithms, in microseconds. Combining FPGA chips with CPUs facilitates their integration with software-oriented devices. This tutorial explores the design of hardware and software architectures that leverage MPSoC (CPU/FPGA Chip) to accelerate an object detection algorithm on the FPGA, while the CPU runs ROS2 nodes for seamless interaction with other components, such as cameras. We will demonstrate the creation of various hardware IPs and the toolchain required to develop drivers for data exchange between the FPGA and CPU. The overall system performance will be evaluated and compared with the classic CPU or GPU implementation of the AI algorithm.
DETAILS
Course type: Tutorial (in person delivery)
Duration: 4 hours
Level: Postgraduate and PhD
Institution of lecturer: Institute of Mechanical and Electrical Engineering, University of Southern Denmark
Notes: The exam will be in the form of a report, where students solve an exercise
Software: Registrants need to install software tools to model AI algorithms and test them in simulation. The software is free of charge.
LECTURER
Prof. Emad Samuel Malki Ebeid